GUWAHATI:
Indian Institute of Technology (IIT) Guwahati is working to develop secure and dependable integrated circuits (ICs) for faster and more efficient computing.
The researchers at the Automation, Verification and Security (AVS) Lab at IIT Guwahati are looking at all aspects of the automated electronics design process like synthesis, verification and security, which contribute towards strengthening the electronics manufacturing ecosystem in our country.
With increasing computational demands, there is a need for application-specific processors that can outperform current CPUs. While multicore processors are being used in modern times, their computing power improvements continue to be insufficient. To cite an analogy for better understanding, running more cars on the road does not necessarily mean you can reach your destination faster; more cars can lead to congestion and delays.
Pointing out the importance and need of research in the area of increasing computational power, Dr Chandan Karfa, said “A promising technology to improve computational efficiency is hardware accelerators. In hardware acceleration, specific tasks can be offloaded to dedicated hardware instead of being performed by the CPU core of the system. For example, visualisation processes may be offloaded onto a graphics card, thereby freeing the CPU to perform other tasks.”
IIT Guwahati team emphasize hardware acceleration specifications that are often written in high-level languages like in C/C++ and are converted to hardware code (or register transfer level or Register-Transfer Level (RTL code), in a process called High-Level Synthesis (HLS). Due to the complex conversation process, HLS translation may introduce bugs in the design and therefore stringent validation steps are required. The RTL simulators are used to validate HLS, but these are slow and complex. The team has developed simple and fast tools for HLS validation.
“We have developed two tools to validate the HLS process. One is FastSim, an RTL simulator that is 300 times faster than existing commercial simulators. The other is DEEQ, which is an automated C to RTL equivalence checking tool for HLS verification. There is no other tool in the market with similar features,” Karfa added.
The findings have been published in top tier journals and conferences of Institute of Electrical and Electronics Engineers (IEEE). The research team is being funded by ECR, CRG and Interdisciplinary Cyber-Physical Systems (ICPS) grants from the Department of Science & Technology, Government of India and by a Research Fellowship from Intel (India).
The paper has been authored by Dr Chandan Karfa, associate professor, Department of Computer Science & Engineering, IIT Guwahati and co-authored by his research students and a few others.